Start of Shift Notes:  

Store 3256 in progress, data taking is paused. 
Bill Badgett is working with physics_test_2_02[10,429,434]

We're having the usual teething pains after the  
TDC DSP programming.   Most pernicious were  
the b0imu00 and b0imu01 crates -- still having  
problems with b0imu01, even after re-reprogramming  
the DSPs.  Argh. 

Am now de-programming the IMU TDCs back to 
the original V37.   Getting them to work tonight 
seems hopeless.

Now deprogramming all but the COT crates -- we have  
enough statistics in the last run to help track  
down the bc mismatch errors in the muon crates. 

Also noticed a large number of crashes at L3.  Not 
clear why.

Starting a new run after deprogramming non-COT TDCs and  
cleaning up the Level 3.    Did not see errors  
from the previous run in COT, so we expect smoother  
running this time.

We disabled the COT HV inhibit after Activate, but 
before any events were taken.

Run looks much smoother now - no spew of TDC error 
messages.

At event 34347 (L2 accept number), I changed the DmaChain  
readout mode to true for crates COT_05 and COT_12 to see  
if that would make any difference in their rate of BC  
mismatch errors.

At event 77109, I changed the DmaChain mode  
for crate COT_16 to true, again to see if that would  
reduce the BC mismatch errors in that crate (as it  
did for COT_05 and COT_12).

The COT crates are now being deprogrammed back  
to their original V37 TDC DSP code version.  All bankVersion  
values have returned to zero. 

The current FrontEndReadout/RunControl package fer  
is now at version v3_24.  All changes are minor,  
and include: 

  . Pick up bug-fix in merlin package that caused low  
    probality of memory heap corruption when creating  
    a merlin message 

  . Fix bug that was suppressing error reporting when  
    the TDC header word in Static RAM did not agree  
    with the header word in the TDC hit FIFO 

  . Patch makefile for newly declared camac product (RLC) 

  . Allow more error message to be reported from frontEnd  
    crates before prescaling them. 

Crates had to be rebooted to pick up the merlin bug fix. 

2nd item above only applies to non-spy-mode readout 
TDC crates.

While waiting for the Level 3 problem to be fixed, I  
loaded the kernel flash RAMs in the SVT_00...07 crates. 
The CDF_VERSION of this kernel is 5.10;  the only real  
difference is that the RTI libraries are now loaded  
so that we can use the HeapCheck() function to verify  
the memory is not corrupted.   This was thanks to  
a work-around from Jim Patrick to load the library  
into large-memory 2304 boards.    So now HEAP_CORRUPT  
errors will be reported from these crates if HeapCheck()  
function indicates a problem with the memory structure. 

Oops, I had the bankVersion=1 still for COTD bank in  
the hdwdb.  I am so bad.  That would cause an increase  
in the Level 3 accept rate as events went to the error  
stream.   However, this should *not* have caused the  
filters to crash...

L3 problems seem to have been resolved

During an interlude, I loaded the new MVME 2401 kernel  
onto the COT crate 01 through 19 flash RAMs.  COT_00 had already  
been running for several days with the new kernel, so we  
were confident that it works fine.  Like the SVT kernel  
load mentioned above, this provides access to the famous 
HeapCheck() function, and allows us to monitor  
the integrity of the memory structure in these crate  
processors. 

Now all but he b0svx## and b0eb## crate processors have  
this checking enabled. 

L3 was paged due to many filters crashing leaving a great part of the farm in a bad state. This
has eventually been realized by Bill Badget as due to a COT related problem. After his COT
corrections, the level3 input rate came down to normal levels, and the crashes were not verified
anymore. The farm is working well.

The conclusion from tonight's beam-on TDC DSP V45 test runs  
was that the COTD bank is ready and working assuming  
the latest L3 tag is used: 

  PHYSICS_TEST_2_02 [10,429,434] 

or any after 434, assuming they have the patch: 

   Level3Filters/src/L3DaqErrorFilter.cc   CVS Revision 1.6 

The problems with the muon crates need further study, but we  
now have more informations to help diagnose the problem. 

Run 179365 was a nice long run with COTD in the new format  
and the rest of the TDC banks in the old format. 

Run 179364 was a useful run to help diagnose the muon crate  
readout problems. 

got vrb evb error: 

Attention!!!. Event Builder SCPU_CANT_RESET_VRB Error !!! 
 THE BAD VRB CRATE is: b0eb16 
 THE BAD VRB MODULE is in SLOT: 10 

reset vrb. back running.

Talked briefly on phone with Bob Wagner. He asks for no more 
tests with Silicon warm so Andy Hocker should start cooling  
Silicon as soon as he shows up this morning. 

Antiproton losses and D0 Roman Pot motion.

CDF    ....     D2    D1         A2     A1    D0    P1    P2

<----- antiproton beam                     proton beam ----->

We started our shift running several tests: 
- Bill Badgett was still working on TDC DSP microcode, facing 
 usual problems with IMU TDC DSP-programming. Finaly he got  
 COTD bank working assuming the latest L3 tag is used  
 PHYSICS_TEST_2_02 [10,429,434]. The problems with the muon   
 crates need further study. 
- 01:00: Vadim & Burkhard are taking some test runs splitting  
 (isolist) fibers  
- 03:00: L3 was paged due to many filters crashing and leaving a  
 great part of the farm in a bad state. This has eventually been 
 realized as due to a COT related problem. After Bill's COT 
 corrections,  L3 farm is working well. 
- 04:30: test run with TEST_ALPHA_CLUSTERING_NOSPIKES[2,430,403], 
 requested by jdl (only 30 min.) 
- 05:00 we only started run with physycs_test_2_02[10,429,433]. 

Runs                   179364-179379
Delivered Luminosity   756.3  
Acquired Luminosity    373.1  
Efficiency             49.3

Marked Bad, explanation:
COT 
SVX 
ISL 
L00 
SVT