While all development up until now has used VME based processors based on the Motorola 68040 architecture (MVME 162s and 167s), the processors to be used in the crates at B0 will be Motorola MVME2301s, based on the Power PC 603 architecture. This has the following compatibility issues:

• There are problems with all released versions of FISION through 2.12 and 2.12a that prevent doing programmed I/O (non-dma) to more than one or two modules in a crate. You must use FISION 2.12b or later, this should be obtained from Fermilab kits.

• Code that runs on unix, Linux, or Windows NT that simply makes FISION calls over the network through the processor should work with no modification.

• For code that performs DMA operations and is built to run directly on the VME processor, the Universe VME interface chip requires that the low 3 bits of the memory address match the low 3 bits of the VME address. By default, single word transfers are done by programmed I/O, and transfers of >= 64 bytes are performed by DMA.

  For example:

  • memory address = 0x00005478 vme address = 0x00800000 - OK
  • memory address = 0x00005478 vme address = 0x00800004 - not allowed
  • memory address = 0x0000547c vme address = 0x00800000 - not allowed.

  The easiest way to ensure the proper alignment is:

  • Ensure that all VME addresses on a board that are appropriate for block transfers have their low 3 bits set to zero. Even if your board is already designed, it is well worth changing it!

  • Only perform block transfers to/from memory allocated by malloc. Such memory blocks will always have the low 3 bits of their address zero. Of course, you must remember to call free to avoid memory leaks which will eventually hang the board. Do not transfer data to/from defined arrays (like int mydata[1000]), as their alignment cannot be specified. This is not a Power PC specific guideline, use of such arrays in VxWorks can be dangerous as stack or global memory overflows may occur without warning.

• True FIFO mode dma operations, where the VME address is held constant for each data transfer, are not supported. This can be dealt with in one of two ways:
  • Modify your board design so that for FIFOs, the low bits of the address are ignored. For example, the VRB and TDC do this for their data FIFOs.
  • Transfer the data by repeated single word transfers. If the module cannot deal with the address changing, then DMA operations cannot be used.

• If the "vme" component is used in the VISIONopen call, it is necessary to include the "/size=xxxxxxxx" parameter. Here, xxxxxxxx should be the largest length you wish to access with a single VISIONread/write call. It is not necessary to include /size= when the "geo32" component is used.

• If a program attempts to delay execution by means of dummy loops etc., these will execute more than a factor of 10 faster on the Power PC. However, code that uses taskDelay() should work the same. Remember, a general guideline (not Power PC specific) is that calling taskDelay(1) has unpredicable behaviour and should not be used.

If you have problems, please send mail to:

• fision-support@fnal.gov for fision problems/questions
• vxworks-support@fnal.gov for vxworks problems/questions